Three-dimensional (3D) circuit integration often includes horizontally and/or vertically stacked devices to provide improved communication between stacked dies and to reduce the area occupied by the stacked devices. For example, coupled layers of memory elements (referred to as 3D stacked memory, or stacked memory) may be utilized in memory devices. With a number of interconnects between a processor and the memory no longer constrained by off-chip pin counts with 3D integration, multiple threads can access stacked memory in parallel to provide higher bandwidth for various compute operations.